Communication system capable of reassigning radio receivers

ABSTRACT

A radio communication system (100) has radio receivers (106) assigned to a predetermined one of a plurality of time periods (FRAME 0-127). The radio communication system (100) comprises a transmitter (104) that transmits information during the predetermined time period (FRAME 0-127) assigned to at least one radio receiver (106). A receiver (202, 206) receives information directed to said at least one radio receivers (106), the radio receivers (106) being individually assigned to receive information during at least one of a plurality of predetermined time periods (FRAME 0-127). A monitoring device (1702) monitors a level of traffic associated with each of the predetermined time periods (FRAME 0-127) and a measuring device (1704) measures a level of traffic associated with the at least one radio receiver (106) over the assigned predetermined time period (FRAME 0-127). An identifying device (1708) which is coupled to the measuring device (1704) identifies if the level of traffic associated with the at least one radio receiver (106) exceeds a predetermined threshold value during the assigned predetermined time period (FRAME 0-127). A generator (1732) which is coupled to the measuring device (1706) and to the identifying device (1708) generates a control signal, and the transmitter (1736) transmits the control signal to the at least one radio receiver (106) for reassigning the at least one radio receiver (106). The at least one radio receiver (106) comprises a receiver (804) which receives the control signal and a decoder (810) which is coupled to the receiver (804) which decodes the control signal. A reassigning device (1812) which is coupled to the decoder (810) reassigns the radio receiver (106) from the assigned predetermined time period (FRAME 0-127) to another of the plurality of predetermined time periods (FRAME 0-127) having a lower level of traffic value associated therewith for reducing the level of traffic in the assigned predetermined time period (FRAME 0-127).

FIELD OF THE INVENTION

This invention relates in general to communication systems; and morespecifically to a communication system capable of reassigning radioreceivers.

BACKGROUND OF THE INVENTION

Current communication systems have endeavored to efficiently communicateinformation to receivers, for example, selective call receivers(pagers), while providing for effective battery saving operations of theselective call receivers. With synchronous signalling and codingformats, receivers are divided into a plurality of frames (e.g.,queues), each frame occurring at a predetermined period and having apredetermined maximum message information capacity, etc. Since thesynchronous signals are always being transmitted, no preamble signalsare required, and the selective call receivers need only to decodepaging information while its preassigned frame is being transmitted.

However, varying traffic demands (the amount of message information fora group of selective call receivers) may cause the amount of messageinformation for one group or queue of selective call receivers to exceedthe maximum capacity of the frame (or queue) while another frame hasavailable capacity. Thus, throughput is decreased by transmitting idlesignals during one frame while another frame has message informationexceeding its capacity.

Also, one or more radio receivers (subscribers) in the communicationsystem may receive excessively long messages or receive messages toofrequently which substantially increase the delay within the systemframe for the other radio receivers that are receiving average lengthand frequency of messages. The resulting increase in length of thesystem queue is undesirable because too long a delay for radio receiversto receive messages within that frame, and any further traffic increaseon that frame will quickly increase the length of the system queuebeyond the system capacity.

Thus, what is needed is a communication system capable of identifyingthe radio receivers that are receiving above-average traffic andreassigning the radio receivers to eliminate imbalances between systemframes of the communication system.

SUMMARY OF THE INVENTION

A radio communication system having radio receivers that are assigned toa predetermined one of a plurality of time periods. The radiocommunication system comprises a transmitter that transmits informationduring the predetermined time period assigned to at least one radioreceiver. A receiver receives information directed to at least one ofthe radio receivers, the radio receivers being individually assigned toreceive the information during at least one of a plurality ofpredetermined time periods. A monitoring means monitors a level oftraffic associated with each of the predetermined time periods and ameasuring means measures a level of traffic associated with at least oneof the radio receivers over the assigned predetermined time period. Anidentifying means which is coupled to the measuring means identifies ifa level of traffic associated with at least one radio receiver exceeds apredetermined threshold value during the assigned predetermined timeperiod. A generating means which is coupled to the measuring means andto the identifying means generates a control signal, and the transmittertransmits the control signal to the at least one radio receiver forreassigning the at least one radio receiver. The at least one radioreceiver comprises a receiver which receives the control signal and adecoder which is coupled to the receiver which decodes the controlsignal. A reassigning means which is coupled to the decoder reassignsthe radio receiver from the assigned predetermined time period toanother of the plurality of predetermined time periods having a lowerlevel of traffic value associated therewith for reducing the level oftraffic in the assigned predetermined time period.

In a radio communication system having subscribers assigned to one of aplurality of predetermined time periods on at least one radio frequency,a method for reassigning the radio receivers, comprising the steps of:

(a) monitoring the level of received information traffic associated witheach of the plurality of predetermined time periods for transmitting toat least one of the plurality of radio receivers;

(b) measuring the level of traffic associated with one or more radioreceivers over the predetermined time period;

(c) determining if one or more of the radio receivers during thepredetermined time period has a traffic level above a threshold value;and

(d) reassigning one or more selected radio receivers to reduce thetraffic level of the predetermined time period when one or more of theradio receivers have a traffic level above the threshold value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical block diagram of a data transmission system inaccordance with the preferred embodiment of the present invention.

FIG. 2 is an electrical block diagram of a terminal for processing andtransmitting message information in accordance with the preferredembodiment of the present invention.

FIGS. 3-5 are timing diagrams illustrating the transmission format ofthe signaling protocol utilized in accordance with the preferredembodiment of the present invention.

FIGS. 6 and 7 are timing diagrams illustrating the synchronizationsignals utilized in accordance with the preferred embodiment of thepresent invention.

FIG. 8 is an electrical block diagram of a data communication receiverin accordance with the preferred embodiment of the present invention.

FIG. 9 is an electrical block diagram of a threshold level extractioncircuit utilized in the data communication receiver of FIG. 8.

FIG. 10 is an electrical block diagram of a 4-level decoder utilized inthe data communication receiver of FIG. 8.

FIG. 11 is an electrical block diagram of a symbol synchronizer utilizedin the data communication receiver of FIG. 8.

FIG. 12 is an electrical block diagram of a 4-level to binary converterutilized in the data communication receiver of FIG. 8.

FIG. 13 is an electrical block diagram of a synchronization correlatorutilized in the data communication receiver of FIG. 8.

FIG. 14 is an electrical block diagram of a phase timing generatorutilized in the data communication receiver of FIG. 8.

FIG. 15 is an electrical block diagram of a data communication receiverwith an acknowledge-back transmitter in accordance with a secondembodiment of the present invention.

FIG. 16 is a flow chart illustrating the synchronization correlationsequence in accordance of the present invention.

FIGS. 17 and 18 are flow diagrams illustrating the reassignment sequenceof the communication system in accordance with the preferred embodimentof the invention.

FIG. 19 is flow diagram illustrating the reassignment sequence of theradio receiver in accordance with the preferred embodiment of theinvention.

DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 is an electrical block diagram of a data transmission system 100,such as a paging system, in accordance with the preferred embodiment ofthe present invention In such a data transmission system 100, messagesoriginating either from a phone, as in a system providing numeric datatransmission, or from a message entry device, such as an alphanumericdata terminal, are routed through the public switched telephone network(PSTN) to a paging terminal 102 which processes the numeric oralphanumeric message information for transmission by one or moretransmitters 104 provided within the system. When multiple transmittersare utilized, the transmitters 104, preferably in simulcast, transmitthe message information to data communication receivers 106. Processingof the numeric and alphanumeric information by the paging terminal 102,and the protocol utilized for the transmission of the messages isdescribed below.

FIG. 2 is an electrical block diagram of the paging terminal 102utilized for processing and controlling the transmission of the messageinformation in accordance with the preferred embodiment of the presentinvention. Short messages, such as tone-only and numeric messages whichcan be readily entered using a Touch-Tone telephone, are coupled to thepaging terminal 102 through a telephone interface 202 in a manner wellknown in the art. Longer messages, such as alphanumeric messages whichrequire the use of a data entry device, are coupled to the pagingterminal 102 through a modem 206 using any of a number of well knownmodem transmission protocols. When a call to place a message isreceived, a controller 204 handles the processing of the message. Thecontroller 204 is preferably a microcomputer, such as an MC68000 orequivalent, which is manufactured by Motorola Inc., and which runsvarious pre-programmed routines for controlling such terminal operationsas voice prompts to direct the caller to enter the message, or thehandshaking protocol to enable reception of messages from a data entrydevice. When a call is received, the controller 204 referencesinformation stored in the subscriber database 208 to determine how themessage being received is to be processed. The subscriber data base 208includes, but is not limited to, such information as addresses assignedto the data communication receiver, message type associated with theaddress, and information related to the status of the data communicationreceiver, such as active or inactive for failure to pay the servicecharges. A data entry terminal 240 is provided which couples to thecontroller 204, and which is used for such purposes as entry, updatingand deleting of information stored in the subscriber data base 208, formonitoring system performance, and for obtaining such information asservice charge information.

The subscriber database 208 also includes such information as to whattransmission frame and to what transmission phase the data communicationreceiver is assigned, as will be described in further detail below. Thereceived message is stored in an active page file 210 which stores themessages in queues according to the transmission phase assigned to thedata communication receiver. In the preferred embodiment of the presentinvention, four phase queues are provided in the active page file 210.The active page file 210 is preferably a dual port, first in first outrandom access memory, although it will be appreciated that other randomaccess memory devices, such as hard disk drives, can be utilized aswell. Periodically ,the message information stored in each of the phasequeues is recovered from the active page file 210 under control ofcontroller 204 using timing information such as provided by a real timeclock 214, or other suitable timing source. The recovered messageinformation from each phase queue is sorted by frame number and is thenorganized by address, message information, and any other informationrequired for transmission, and then batched into frames based uponmessage size by frame batching controller 212. The batched frameinformation for each phase queue is coupled to frame message buffers 216which temporarily store the batched frame information until a time forfurther processing and transmission. Frames are batched in numericsequence, so that while a current frame is being transmitted, the nextframe to be transmitted is in the frame message buffer 216, and the nextframe thereafter is being retrieved and batched. At the appropriatetime, the batched frame information stored in the frame message buffer216 is transferred to the frame encoder 218, again maintaining the phasequeue relationship. The frame encoder 218 encodes the address andmessage information into address and message code words required fortransmission, as will be described below. The encoded address andmessage code words are ordered into blocks and then coupled to a blockinterleaver 220 which interleaves preferably eight code words at a timefor transmission in a manner well known in the art. The interleaved codewords from each block interleaver 220 are then serially transferred to aphase multiplexer 221, which multiplexes the message information on abit by bit basis into a serial data stream by transmission phase. Thecontroller 204 next enables a frame sync generator 222 which generatesthe synchronization code which is transmitted at the start of each frametransmission. The synchronization code is multiplexed with address andmessage information under the control of controller 204 by serial datasplicer 224, and generates therefrom a message stream which is properlyformatted for transmission. The message stream is next coupled to atransmitter controller 226, which under the control of controller 204transmits the message stream over a distribution channel 228. Thedistribution channel 228 may be any of a number of well knowndistribution channel types, such as wire line, an RF or microwavedistribution channel, or a satellite distribution link. The distributedmessage stream is transferred to one or more transmitter stations 104,depending upon the size of the communication system. The message streamis first transferred into a dual port buffer 230 which temporarilystores the message stream prior to transmission. At an appropriate timedetermined by timing and control circuit 232, the message stream isrecovered from the dual port buffer 230 and coupled to the input ofpreferably a 4-level FSK modulator 234. The modulated message stream isthen coupled to the transmitter 236 for transmission via antenna 238.

FIGS. 3, 4 and 5 are timing diagrams illustrating the transmissionformat of the signaling protocol utilized in accordance with thepreferred embodiment of the present invention. As shown in FIG. 3, thesignaling protocol enables message transmission to data communicationreceivers such as pagers, assigned to one or more of 128 frames whichare labeled frame 0 through frame 127. It then will be appreciated thatthe actual number of flames provided within the signaling protocol canbe greater or less than described above. The greater the number offrames utilized, the greater the battery life that may be provided tothe data communication receivers operating within the system. The fewerthe number of frames utilized, the more often messages can be queued anddelivered to the data. Communication receivers assigned to anyparticular frame, thereby reducing the latency, or time required todeliver messages.

As shown in FIG. 4, the frames comprise a synchronization code (sync)followed preferably by eleven blocks of message information which arelabeled block 0 through block 10. As shown in FIG. 5, each block ofmessage information comprises preferably eight address, control or datacode words which are labeled word 0 through word 7 for each phase.Consequently, each phase in a frame allows the transmission of up toeighty-eight address, control and data code words. The address, controland data code words are preferably 31,21 BCH code words with an addedthirty-second even parity bit which provides an extra bit of distance tothe code word set. It will be appreciated that other code words, such asa 23,12 Golay code word could be utilized as well. Unlike the well knownPOCSAG signaling protocol which provides address and data code wordsthat utilize the first code word bit to define the code word type, aseither address or data, no such distinction is provided for the addressand data code words in the signaling protocol utilized with thepreferred embodiment of the present invention. Rather, address and datacode words are defined by their position within the individual frames.

FIGS. 6 and 7 are timing diagrams illustrating the synchronization codeutilized in accordance with the preferred embodiment of the presentinvention. In particular, as shown in FIG. 6, the synchronization codecomprises preferably three parts, a first synchronization code (sync 1),a frame information code word (frame info) and a second synchronizationcode (sync 2). As shown in FIG. 7, the first synchronization codecomprises first and third portions, labeled bit sync 1 and BS1, whichare alternating 1,0 bit patterns which provides bit synchronization, andsecond and fourth portions, labeled "A" and its complement "A bar",which provide frame synchronization. The second and fourth portions arepreferably single 32,21 BCH code words which are predefined to providehigh code word correlation reliability, and which are also used toindicate the data bit rate at which addresses and messages aretransmitted. The table below defines the data bit rates which are usedin conjunction with the signaling protocol.

    ______________________________________                                        Bit Rate      "A" Value                                                       ______________________________________                                        1600 bps      A1 and A1 bar                                                   3200 bps      A2 and A2 bar                                                   6400 bps      A3 and A3 bar                                                   Not defined   A4 and A4 bar                                                   ______________________________________                                    

As shown in the table above, three data bit rates are predefined foraddress and message transmission, although it will be appreciated thatmore or less data bit rates can be predefined as well, depending uponthe system requirements. A fourth "A" value is also predefined forfuture use.

The frame information code word is preferably a single 32,21 BCH codeword which includes within the data portion a predetermined number ofbits reserved to identify the frame number, such as 7 bits encoded todefine frame number 0 to frame number 127.

The structure of the second synchronization code is preferably similarto that of the first synchronization code described above. However,unlike the first synchronization code which is preferably transmitted ata fixed data symbol rate, such as 1600 bps (bits per second), the secondsynchronization code is transmitted at the data symbol rate at which theaddress and messages are to be transmitted in any given frame.Consequently, the second synchronization code allows the datacommunication receiver to obtain "fine" bit and frame synchronizationthe frame transmission data bit rate.

In summary, the signaling protocol utilized with the preferredembodiment of the present invention comprises 128 frames which include apredetermined synchronization code followed by eleven data blocks whichcomprise eight address, control or message code words per phase. Thesynchronization code enables identification of the data transmissionrate, and insures synchronization by the data communication receiverwith the data code words transmitted at the various transmission rates.

FIG. 8 is an electrical block diagram of the data communication receiver106 in accordance with the preferred embodiment of the presentinvention. The heart of the data communication receiver 106 is acontroller 816, which is preferably implemented using an MC68HC05HC11microcomputer, such as manufactured by Motorola, Inc. The microcomputercontroller, hereinafter call the controller 816, receives and processesinputs from a number of peripheral circuits, as shown in FIG. 8, andcontrols the operation and interaction of the peripheral circuits areachieved by using software subroutines. The use of a microcomputercontroller for processing and control functions is well known to one ofordinary skill in the art.

The data communication receiver 106 is capable of receiving address,control and message information, hereafter called "data" which ismodulated using preferably 2-level and 4-level frequency modulationtechniques. The transmitted data is intercepted by an antenna 802 whichcouples to the input of a receiver section 804. Receiver section 804processes the received data in a manner well known in the art, providingat the output an analog 4-level recovered data signal, hereafter calleda recovered data signal. The recovered data signal is coupled to oneinput of a threshold level extraction circuit 808, and to an input of a4-level decoder 810. The threshold level extraction circuit 808 is bestunderstood by referring to FIG. 9, and as shown, comprises two clockedlevel detector circuits 902, 904 which have as inputs the recovered datasignal. Level detector 902 detects the peak signal amplitude value andprovides a high peak threshold signal which is proportional to thedetected peak signal amplitude value, while level detector 904 detectsthe valley signal amplitude value and provides a valley threshold signalwhich is proportional to the detected valley signal amplitude value ofthe recovered data signal. The level detector 902, 904 signal outputsare coupled to terminals of resistors 906, 912, respectively. Theopposite resistor terminals 906, 912 provide the high threshold outputsignal (Hi), and the low threshold output signal (Lo), respectively. Theopposite resistor terminals 906, 912 are also coupled to terminals ofresistors 908, 910, respectively. The opposite resistor 908, 910terminals are coupled together to form a resistive divider whichprovides an average threshold output signal (Avg) which is proportionalto the average value of the recovered data signal. Resistors 906, 912have resistor values preferably of 1R, while resistors 908, 910 haveresistor values preferably of 2R, realizing threshold output signalvalues of 17%, 50% and 83%, and which are utilized to enable decodingthe 4-level data signals as will be described below.

When power is initially applied to the receiver portion, as when thedata communication receiver is first turned on, a clock rate selector914 is preset through a control input (center sample) to select a 128×clock, i.e. a clock having a frequency equivalent to 128 times theslowest data bit rate, which as described above is 1600 bps. The 128×clock is generated by 128× clock generator 844, as shown in FIG. 8,which is preferably a crystal controlled oscillator operating at 204.8kHz (kiloHertz). The output of the 128× clock generator 844 couples toan input of frequency divider 846 which divides the output frequency bytwo to generate a 64× clock at 102.4 kHz. Returning to FIG. 9, the 128×clock allows the level detectors 902, 904 to asynchronously detect in avery short period of time the peak and valley signal amplitude values,and to therefore generate the low (Lo), average (Avg) and high (Hi)threshold output signal values required for modulation decoding. Aftersymbol synchronization is achieved with the synchronization signal, aswill be described below, the controller 816 generates a second controlsignal (Center Sample) to enable selection of a 1× symbol clock which isgenerated by symbol synchronizer 812 as shown in FIG. 8.

Returning to FIG. 8, the 4-level decoder 810 operation is bestunderstood by referring to FIG. 10. As shown, the 4-level decoder 810comprises three voltage comparators 1010, 1020, 1030 and a symboldecoder 1040. The recovered data signal couples to an input of the threecomparators 1010, 1020, 1030. The high threshold output signal (Hi)couples to the second input of comparator 1010, the average thresholdoutput signal (Avg) couples to the second input of comparator 1020, andthe low threshold output signal (Lo) couples to the second input ofcomparator 1030. The outputs of the three comparators 1010, 1020, 1030couple to inputs of symbol decoder 1040. The symbol decoder 1040 decodesthe inputs according to the table provided below.

    ______________________________________                                        Threshold                  Output                                             Hi        Avg      Lo          MSB  LSB                                       ______________________________________                                        RC.sub.in <                                                                             RC.sub.in <                                                                            RC.sub.in < 0    0                                         RC.sub.in <                                                                             RC.sub.in <                                                                            RC.sub.in > 0    1                                         RC.sub.in <                                                                             RC.sub.in >                                                                            RC.sub.in > 1    1                                         RC.sub.in >                                                                             RC.sub.in >                                                                            RC.sub.in > 1    0                                         ______________________________________                                    

As shown in the table above, when the recovered data signal (RC_(in)) isless than all three threshold values, the symbol generated is 00 (MSB=0,LSB=0). Thereafter, as each of the three threshold values is exceeded, adifferent symbol is generated, as shown in the table above.

The MSB output from the 4-level decoder 810 is coupled to an input ofthe symbol synchronizer 812 and provides a recovered data inputgenerated by detecting the zero crossings in the 4-level recovered datasignal. The positive level of the recovered data input represents thetwo positive deviation excursions of the analog 4-level recovered datasignal above the average threshold output signal, and the negative levelrepresents the two negative deviation excursions of the analog 4-levelrecovered data signal below the average threshold output signal.

The operation of the symbol synchronizer 812 is best understood byreferring to FIG. 11. The 64× clock at 102.4 kHz which is generated byfrequency divider 846, is coupled to an input of a 32× rate selector1120. The 32× rate selector 1120 is preferably a divider which providesselective division by 1 or 2 to generate a sample clock which isthirty-two times the symbol transmission rate. A control signal(1600/3200) is coupled to a second input of the 32× rate selector 1120,and is used to select the sample clock rate for symbol transmissionrates of 1600 and 3200 symbols per second. The selected sample clock iscoupled to an input of 32× data oversampler 1110 which samples therecovered data signal (MSB) at thirty-two samples per symbol. The symbolsamples are coupled to an input of a data edge detector 1130 whichgenerates an output pulse when a symbol edge is detected. The sampleclock is also coupled to an input of a divide-by-16/32 circuit 1140which is utilized to generate 1× and 2× symbol clocks synchronized tothe recovered data signal. The divided-by-16/32 circuit 1140 ispreferably an up/down counter. When the data edge detector 1130 detectsa symbol edge, a pulse is generated which is gated by AND gate 1150 withthe current count of divide-by-16/32 circuit 1140. Concurrently, a pulseis generated by the data edge detector 1130 which is also coupled to aninput of the divide-by-16/32 circuit 1140. When the pulse coupled to theinput of AND gate 1150 arrives before the generation of a count ofthirty-two by the divide-by-16/32 circuit 1140, the output generated byAND gate 1150 causes the count of divide-by-16/32 circuit 1140 to beadvanced by one count in response to the pulse which is coupled to theinput of divide-by-16/32 circuit 1140 from the data edge detector 1130,and when the pulse coupled to the input of AND gate 1150 arrives afterthe generation of a count of thirty-two by the divide-by-16/32 circuit1140, the output generated by AND gate 1150 causes the count ofdivide-by-16/32 circuit 1140 to be retarded by one count in response tothe pulse which is coupled to the input of divide-by-16/32 circuit 1140from the data edge detector 1130, thereby enabling the synchronizationof the 1× and 2× symbol clocks with the recovered data signal. Thesymbol clock rates generated are best understood from the table below.

    ______________________________________                                                         Rate            2×                                                                             1×                              Input   Control  Selector Rate   Symbol Symbol                                Clock   Input    Divide   Selector                                                                             Clock  Clock                                 (Relative)                                                                            (SPS)    Ratio    Output (BPS)  (BPS)                                 ______________________________________                                        64×                                                                             1600     by 2     32×                                                                            3200   1600                                  64×                                                                             3200     by 1     64×                                                                            6400   3200                                  ______________________________________                                    

As shown in the table above, the 1× and 2× symbol clocks are generatedat 1600, 3200 and 6400 bits per second and are synchronized with therecovered data signal.

The 4-level binary converter 814 is best understood by referring to FIG.12. The 1× symbol clock is coupled to a first clock input of a clockrate selector 1210. A 2× symbol clock also couples to a second clockinput of the clock rate selector 1210. The symbol output signals (MSB,LSB) are coupled to inputs of an input data selector 1230. A selectorsignal (2L/4L) is coupled to a selector input of the clock rate selector1210 and the selector input of the input data selector 1230, andprovides control of the conversion of the symbol output signals aseither 2-level FSK data, or 4-level FSK data. When the 2-level FSK dataconversion (2L) is selected, only the MSB output is selected which iscoupled to the input of a parallel to serial converter 1220. The 1×clock input is selected by clock rate selector 1210 which results in asingle bit binary data stream to be generated at the output of theparallel to serial converter 1220. When the 4-level FSK data conversion(4L) is selected, both the LSB and MSB outputs are selected which arecoupled to the inputs of the parallel to serial converter 1220. The 2×clock input is selected by clock rate selector 1210 which results in aserial two bit binary data stream to be generated at 2× the symbol rate,which is provided at the output of the parallel to serial converter1220.

Returning to FIG. 8, the serial binary data stream generated by the4-level to binary converter 814 is coupled to inputs of asynchronization word correlator 818 and a demultiplexer 820. Thesynchronization word correlator is best understood with reference toFIG. 13. Predetermined "A" word synchronization patterns are recoveredby the controller 816 from a code memory 822 and are coupled to an "A"word correlator 1310. When the synchronization pattern received matchesone of the predetermined "A" word synchronization patterns within anacceptable margin of error, an "A" or "A-bar" output is generated and iscoupled to controller 816. The particular "A" or "A-bar" wordsynchronization pattern correlated provides frame synchronization to thestart of the frame ID word, and also defines the data bit rate of themessage to follow, as was previously described.

The serial binary data stream is also coupled to an input of the frameword decoder 1320 which decodes the frame word and provides anindication of the frame number currently being received by thecontroller 816. During sync acquisition, such as following initialreceiver turn-on, power is supplied to the receiver portion by batterysaver circuit 848, shown in FIG. 8, which enabled the reception of the"A" synchronization word, as described above, and which continues to besupplied to enable processing of the remainder of the synchronizationcode. The controller 816 compares the frame number currently beingreceived with a list of assigned frame numbers stored in code memory822. Should the currently received frame number differ from an assignedframe numbers, the controller 816 generates a battery saving signalwhich is coupled to an input of battery saver circuit 848, suspendingthe supply of power to the receiver portion. The supply of power will besuspended until the next frame assigned to the receiver, at which time abattery saver signal is generated by the controller 816 which is coupledto the battery saving circuit 848 to enable the supply of power to thereceiver portion to enable reception of the assigned frame.

Returning to the operation of the synchronization correlator shown inFIG. 13, a predetermined "C" word synchronization pattern is recoveredby the controller 816 from a code memory 822 and is coupled to a "C"word correlator 1330. When the synchronization pattern received matchesthe predetermined "C" word synchronization pattern with an acceptablemargin of error, a "C" or "C-bar" output is generated which is coupledto controller 816. The particular "C" or "C-bar" synchronization wordcorrelated provides "fine" frame synchronization to the start of thedata portion of the frame.

Returning to FIG. 8, the start of the actual data portion is establishedby the controller 816 generating a block start signal (Blk Start) whichis coupled to inputs of a word de-interleaver 824 and a data recoverytiming circuit 826. The data recovery timing circuit 826 is bestunderstood by referring to FIG. 14. A control signal (2L/4L) is coupledto an input of clock rate selector 1410 which selects either 1X or 2Xsymbol clock inputs. The selected symbol clock is coupled to the inputof a phase generator 1430 which is preferably a clocked ring counterwhich is clocked to generate four phase output signals (φ1-φ4). A blockstart signal (BLK START) is also coupled to an input of the phasegenerator 1430, and is used to hold the ring counter in a predeterminedphase until the actual decoding of the message information is to begin.When the block start signal releases the phase generator 1430, the phasegenerator 1430 begins generating clocked phase signals which aresynchronized with the incoming message symbols.

Referring back to FIG. 8, the clocked phase signal outputs are coupledto inputs of a phase selector 828. During operation, the controller 816recovers from the code memory 822, the transmission phase number towhich the data communication receiver is assigned. The phase number istransferred to the phase select output (φ Select) of the controller 816and is coupled to an input of phase selector 828. A phase clock,corresponding to the transmission phase assigned, is provided at theoutput of the phase selector 828 and is coupled to clock inputs of thedemultiplexer 820, block de-interleaver 824, and address and datadecoders 830 and 832, respectively. The demultiplexer 820 is used toselect the binary bits associated with the assigned transmission phasewhich are then coupled to the input of block de-interleaver 824, andclocked into the de-interleaver array on each corresponding phase clock.The de-interleaver array is an 8×32 bit array which de-interleaves eightinterleaved address, control or message code words, corresponding to onetransmission block. The de-interleaved address code words are coupled tothe input of address correlator 830. The controller 816 recovers theaddress patterns assigned to the data communication receiver, andcouples the patterns to a second input of the address correlator. Whenany of the de-interleaved address code words matches any of the addresspatterns assigned to the data communication receiver within anacceptable margin of error, the message information associated with theaddress is then decoded by the data decoder 832 and stored in a messagememory 850 in a manner well known to one of ordinary skill in the art.Following the storage of the message information, a sensible alertsignal is generated by the controller 816. The sensible alert signal ispreferably an audible alert signal, although it will be appreciated thatother sensible alert signals, such as tactile alert signals and visualalert signals can be generated as well. The audible alert signal iscoupled by the controller 816 to an alert driver 834 which is used todrive an audible alerting device, such as a speaker or a transducer 836.The user can override the alert signal generation through the use ofuser input controls 838 in a manner well known in the art.

Following the detection of an address associated with the datacommunication receiver, the message information is coupled to the inputof data decoder 832 which decodes the encoded message information intopreferably a BCD or ASCII format suitable for storage and subsequentdisplay. The stored message information can be recalled by the userusing the user input controls 838 whereupon the controller 816 recoversthe message information from memory, and provides the messageinformation to a display driver 840 for presentation on a display 842,such as an LCD display.

FIG. 15 is an electrical block diagram of a second embodiment of thedata communication receiver 106 shown in FIG. 8. The structure andoperation remains substantially the same as shown in FIG. 8, but for thedifferences which will be illustrated below. Specifically, according tothe second embodiment shown in FIG. 15, the antenna 802 is coupled to anantenna switch 854 which enables the antenna 802 to be switched betweenreceiving and transmitting modes, a technique which is well known tothose skilled in the art. An acknowledge-back transmitter 856 is coupledto the antenna switch 854 and the controller/memory/driver circuitembodied in block 800. Operationally, when the data communicationreceiver 106 is receiving data, the antenna switch 854 is switched bythe controller 816 (shown in FIG. 8 and embodied in block 800) to thereceiving mode, and the data received by the antenna 802 is passed tothe receiver 804 as discussed in FIG. 8. When the data communicationreceiver 106 is transmitting data (e.g., an acknowledge-back response aswill be described below), the controller 816 switches the antenna switch854 to the transmitting mode, and the data is passed from the controller816 via the acknowledge-back transmitter 856 and is transmitted by theantenna 802.

FIG. 16 is a flow chart describing the operation of the datacommunication receiver in accordance with the preferred embodiment ofthe present invention. At step 1502, when the data communicationreceiver is turned on, the controller operation is initialized, at step1504. Power is periodically applied to the receiver portion to enablereceiving information present on the assigned RF channel. When data isnot detected on the channel in a predetermined time period, batterysaver operation is resumed, at step 1508. When data is detected on thechannel at step 1506, the synchronization word correlator beginssearching for bit synchronization at step 1510. When bit synchronizationis obtained, at step 1510, the "A" word correlation begins at step 1512.When the noncomplemented "A" word is detected, at step 1514, the messagetransmission rate is identified as described above, at step 1516, andbecause frame synchronization is obtained, the time (T1) to the start ofthe frame identification code word is identified, at step 1518. When thenoncomplemented "A" word is not detected, at step 1514, indicating thenoncomplemented "A" word may have been corrupted by a burst error duringtransmission, a determination is made whether the complemented "A" bar"is detected, at step 1520. When the "A bar" word is not detected at step1520, indicating that the "A-bar" word may also have been corrupted by aburst error during transmission, battery saver operation is againresumed, at step 1508. When the "A-bar" word is detected, at step 1520,the message transmission rate is identified as described above, at step1522, and because frame synchronization is obtained, the time (T2) tothe start of the frame identification code word is identified, at step1524. At the appropriate time, decoding of the frame identification wordoccurs, at step 1526. When the frame ID detected is not one assigned tothe data communication receiver, at step 1528, battery saving isresumed, at step 1508, and remains so until the next assigned frame isto be received. When the decoded frame ID corresponds to an assignedframe ID, at step 1528, the message reception rate is set, at step 1530.An attempt to bit synchronize at the message transmission rate is nextmade at step 1532. When bit synchronization is obtained, at step 1533,the "C" word correlation begins at step 1534. When the non-complemented"C" word is detected., at step 1536, frame synchronization is obtained,and the time (T3) to the start of the message information is identified,at step 1538.

When the non-complemented "C" word is not detected, at step 1536,indicating the non-complemented "C" word may have been corrupted by aburst error during transmission, a determination is made whether thecomplement "C-bar" is detected, at step 1540. When the "C-bar" word isnot detected at step 1540, indicating that the "C-bar" word may alsohave been corrupted by a burst error during transmission, battery saveroperation is again resumed, at step 1508. When the "C-bar" word isdetected, at step 1540, frame synchronization is obtained, and the time(T4) to the start of the message information is identified, at step1542. At the appropriate time, message decoding can begin at step 1544.

In code words which are spaced in time, the reliability of synchronizingwith synchronization information that is subject to burst errorcorruption is greatly enhanced. The use of a predeterminedsynchronization code word as the first synchronization code word, and asecond predetermined synchronization code word which is the complementof the first predetermined synchronization code word, allow accurateframe synchronization on either the first or the second predeterminedsynchronization code word. By encoding the synchronization code words,additional information, such as the transmission data rate, can beprovided, thereby enabling the transmission of message information atseveral data bit rates. By using a second coded synchronization wordpair, "fine" frame synchronization at the actual message transmissionrate can be achieved, and as above, due to spacing in time of thesynchronization code words, the reliability of synchronizing at adifferent data bit rate with synchronization information which issubject to burst error corruption is greatly enhanced, thereby improvingthe reliability of the data communication receiver to receive andpresent messages to the receiver user.

FIGS. 17 and 18 are flow diagrams illustrating the reassignment sequenceby the communication system in accordance with the preferred embodimentof the invention. Specifically referring to FIG. 17, after thesynchronization sequence, the communication system, for example, thepaging terminal or base station, monitors traffic intended for the radioreceivers that are active during each of the predetermined time periodsto determine the traffic intended during each of the predetermined timeperiods, step 1702. That is, step 1702 monitors the traffic in thequeues of the communication system of each predetermined time periods.Frames and phases are described above in FIG. 3, and time periods orpredetermined time periods are used hereafter to refer to flames and/orphases because one of ordinary skill in the art will appreciate thatframes or phases are predetermined time periods. Also, the level oftraffic in a predetermined time period is determined by a measure of thetime of the intended information and the length of the predeterminedtime period. Thus, the level of traffic for each predetermined timeperiod is the calculated average of the time of the intended informationtime divided by the predetermined time period. Alternately, the trafficlevel can be determined by counting data elements (e.g., data bits,characters, or a measure of the time information is present during thepredetermined time period). Step 1704 determines the radio receiversthat are most active during the predetermined time periods. The activityof the radio receivers are determined by a product of the number ofcalls received by that radio receiver (i.e., call rate) and the numberof call elements (e.g., number of characters of total information, thenumber of bits of information, etc.). The average queue length of eachtime period is then determined for each time period which generallyincludes a determination for each frame or for each phase, step 1706.The time periods with the lowest average queue length (minimum trafficduring the predetermined time period) are then identified, step 1708. Instep 1710, a file history of the most active radio receivers during eachof the predetermined time periods is created to facilitate reassignmentof radio receivers when needed. Subsequent to the creation of the filehistory, the system determines when any predetermined time period has atraffic level greater than the average system traffic level percentagefor that time period, step 1712. If no, the system returns to step 1702.When yes, the traffic level for that predetermined time period which isgreater than the system traffic level is identified, step 1714. Next,the system determines if any radio receivers' traffic levels are greaterthan the threshold value for the radio receivers, step 1716. Thisthreshold value is preferably a chosen percentage above the averagequeue length for all radio receivers within the predetermined timeperiods. Alternatively, the threshold value can be a chosen percentageabove the average queue length for all radio receivers within thecommunication system. When a particular radio receiver's traffic levelis not greater than the threshold value calculated for the radioreceiver, the system flow returns to step 1702 to continue to monitorradio receivers' activity.

In FIG. 18, the flow diagram continues at step 1718 where the radioreceivers identified with traffic levels above the system plan (e.g.,traffic level above a threshold value of time use for the predeterminedtime period) are indicated. Then in step 1720, the system selects aradio receiver as a candidate to be reassigned and creates a list ofradio receivers that are selected. The radio receivers can be selectedfrom, for example, the radio receivers that subscribe to a high dataservice such as graphics or alphanumeric, etc. Alternatively, the radioreceivers can be selected from the radio receivers identified with atraffic level above the traffic level threshold value or because theradio receivers were identified with a traffic level below the trafficlevel threshold value. Any of the above criteria for selecting a radioreceiver as a candidate to be assigned may approximate the same resultbut with a different amount of computation involved in achieving abalanced traffic level among the plurality of predetermined timeperiods. A balanced traffic level is achieved when all 128 frames ortime periods have approximately the same amount of traffic or queuelength or when none of the predetermined time periods have a trafficlevel that exceeds the average system plan traffic level.

According to the preferred embodiment of the present invention, a radioreceiver with an indicated above average traffic level is selected to bereassigned. After selecting the radio receiver, step 1722 determineswhether that radio receiver has been reassigned before within apredetermined length of time. If so, that selected radio receiver isremoved from the list of radio receivers to be reassigned, step 1724,and the flow returns to step 1720 where the system selects another radioreceiver with above threshold traffic level or time use. Alternately,when the selected radio receiver was not reassigned before, the systemdetermines if the selected radio receiver is assigned to a group withother radio receivers, step 1726. When that radio receiver is a memberof a group of radio receivers, then the other members of that groupwould also have to be reassigned. Therefore, when the radio receiver isa member of a group of radio receivers, then that selected radioreceiver is removed from the reassignment list to simplify thereassignment sequence, step 1724, and then the flow returns to step 1720where the system selects another radio receiver with above thresholdtraffic level or time use. Reassigning radio receivers that are membersof a group of radio receivers would frustrate the reassignment of radioreceivers in achieving a balance in the traffic on the plurality of timeperiods because the increase in the number of calculations (e.g., onefor each radio receiver of the group) would over-burden the system toreassign all the members of the group.

Alternately, when the selected radio receiver is not a member of agroup, the traffic level is estimated or calculated without any trafficcontribution of the selected radio receiver to that predetermined timeperiod at the time of calculation, step 1728. At step 1730, theestimated traffic level without the traffic contribution of the selectedradio receiver is determined to ensure that the removal of the selectedradio receiver from that predetermined time period will reduce thetraffic level of that time period to approach the average of the systemtraffic level. In this way, the effect of the removal of the radioreceiver from that predetermined time period is determined before theactual reassignment to ensure that the reassignment reduces the trafficlevel of that predetermined time period. The radio receiver's traffic isalso estimated in other predetermined time periods, preferablypredetermined time periods with below traffic level below averagetraffic levels. An estimate of the placement of the radio receiverwithin another time period is also determined so that the reassignmentof the selected radio receiver does not cause another predetermined timeperiod to which it will be reassigned to exceed the traffic level forthe system plan. If not, the selected radio receiver is removed from thelist, step 1724, and another radio receiver with average traffic abovethe system plan is selected, step 1720. If the selected radio receiverwas determined to reduce the traffic level to approach the satisfactionof the system traffic level, a request for reassignment is transmittedto the radio receiver, step 1732. The system terminal then waits for aresponse, preferably by telephone, from the user of the radio receiverto indicate the receipt of the request for reassignment, step 1734. Whenno response is received within the period for response, the selectedradio receiver is removed from the list, step 1724, and another radioreceiver with average traffic above the system plan is selected, step1720. Alternatively, when the user of the radio receiver responds, thesystem transmits a reassignment control signal to the selected radioreceiver, step 1736. The system then waits for a verification of asuccessful reassignment of the radio receiver, preferably from the userof the radio receiver, step 1738. If the reassignment was unsuccessful,the reassignment code is retransmitted, step 1732. Upon a successfulreassignment, the radio receiver is removed from the list of radioreceivers to be reassigned, step 1740, and a file history is created forthe radio receivers that were reassigned to another predetermined timeperiod, step 1742. The sequence discussed in FIGS. 17 and 18 is repeateduntil each time period is within a specified increment in traffic levelvariation which is determined to approximate a balanced traffic levelduring each of the plurality of time periods.

Reassigning a radio receiver with an acknowledge-back transmitter wouldeliminate the need for the user of the radio receiver to call the systemadministrator to coordinate the reassignment procedure. With theacknowledge-back transmitter, the radio receiver transmits a responseafter receiving the request for reassignment. This acknowledge-backresponse confirms that the radio receiver received that request forreassignment. Upon receipt of the acknowledge-back response by thesystem, the reassignment control signal is then sent to the radioreceiver to reassign the radio receiver. When the radio receiverreceives the control signal, the radio receiver is reassigned orreprogrammed to receive information during another predetermined timeperiod. The system then sends a signal to the radio receiver during thereassigned predetermined time period, and when the signal issuccessfully received by the radio receiver, the acknowledge-backtransmitter responds by transmitting a signal to the terminal toindicate successful reassignment of the radio receiver.

Referring to FIG. 19, a flow diagram is shown illustrating thereassignment sequence of the radio receiver in accordance with thepreferred embodiment of the invention. In step 1802, the radio receiverreceives the request for reassignment, and displays informationcontained therein to a user of the radio receiver, step 1804. Aresponse, preferably within a few minutes, to the request forreassignment is transmitted to the paging terminal, preferably to theadministrator, step 1806. That is, the user of the radio receiver viatelephone contacts the system administrator or service provider. Theradio receiver then receives the control signal transmitted by thepaging terminal, step 1808, and decodes the control signal to determineanother one of the plurality of predetermined time periods forreassigning the radio receiver, step 1810. In step 1812, the radioreceiver is reprogrammed by the received control signal and thusreassigned to the predetermined time period designated by the controlsignal. Subsequent to reassignment, the radio receiver receives averification signal on the reassigned predetermined time period, step1814, and displays the information contained therein which verifies asuccessful reassignment of the radio receiver, step 1816. After receiptof the verification signal, the user of the radio receiver acknowledgeswhether or not the verification signal was successfully received, step1818.

According to the preferred embodiment of the present invention, thefollowing sequence of steps are performed: First, a request istransmitted to the radio receiver to be assigned which is received bythe radio receiver. The paging terminal waits an appropriate length oftime for a response from the radio receiver. When a response isreceived, a system administrator causes the transmission of thereassignment control signal to the selected radio receiver as in step1736. The radio receiver will also display received characters or datawhich will be verified by the user and the system administrator via atelephone call by the user of the radio receiver as in step 1804. Whenthe reassignment sequence (control signal) is correctly received, theradio receiver will reprogram the radio receiver to interrogate anothertime period for its address and other data information, step 1812. Uponverification, the same characters or data will again be sent to theradio receiver addressed during the reassigned (the new) predeterminedtime period. Upon verification of the receipt of the retransmitted dataagain, the radio receiver will then have been successfully reassigned tothe new time period which is determined to approach a balance of thetraffic level between the plurality of predetermined time periods in thesystem, step 1818.

The communication system, as described above, has the capability forreassigning radio receivers that are measured to have a traffic levelabove a threshold value for radio receivers during a predetermined timeperiod which also has a traffic level above the system plan trafficlevel while other predetermined time periods have traffic level belowthe system plan. A balanced communication system is desired because abalanced communication system has a high throughput. This is approachedby constantly checking the plurality of predetermined time periods toensure that information instead of idle bits are being transmitted. As aresult, subscribers of the radio receivers may be charged a lowerair-time fee because of the increased efficiency of the balanced systemresults in no or fewer idle bits being transmitted while otherpredetermined time period have an overloaded queue. Thus, withreassignment capability, the system determines which of thepredetermined time periods have above average traffic levels and whichpredetermined time periods have below average traffic. Upon selectingappropriate radio receivers to be reassigned, preferably a radioreceiver with above average system plan traffic level, the system isable to reassign the selected radio receivers to other predeterminedtime periods with below average system plan traffic level to eliminateidle time and excessive queueing on the plurality of predetermined timeperiods. In this way, the communication system is able to maintain abalanced traffic level on the plurality of predetermined time periods byredistributing the traffic to the plurality of predetermined timeperiods thereby eliminating the idle time periods and queueing on theplurality of predetermined time periods which results in higherinformation efficiency within the communication system which ultimatelyresults in lower air-time charges to subscribers.

We claim:
 1. A radio communication system having radio receiversassigned to a predetermined one of a plurality of predetermined timeperiods, comprising:transmitting means for transmitting informationduring the predetermined one of the plurality of predetermined timeperiods assigned to at least one radio receiver; receiving means forreceiving information directed to said at least one radio receiver, saidat least one radio receiver being individually assigned to receive theinformation during the predetermined one of the plurality ofpredetermined time periods; means for monitoring a level of trafficassociated with each of the plurality of predetermined time periods;means for measuring a level of traffic associated with said at least oneradio receiver during the predetermined one of the plurality ofpredetermined time periods assigned to said at least one selective callreceiver; means, coupled to said measuring means, for identifying if thelevel of traffic associated with said at least one radio receiverexceeds a predetermined threshold value during the predetermined one ofthe plurality of predetermined time periods; means, coupled to saidmeasuring means and to said identifying means, for generating a controlsignal; said transmitting means for transmitting the control signal tosaid at least one radio receiver, said at least one radio receivercomprising:means for receiving said control signal; means, coupled tosaid receiving means, for decoding said control signal; and reassigningmeans, coupled to said decoding means, for reassigning said at least oneradio receiver from said predetermined one of a plurality ofpredetermined time periods to another of the plurality of predeterminedtime periods having a lower level of traffic value associated therewithfor reducing the level of traffic in said predetermined one of theplurality of predetermined time periods.
 2. The communication systemaccording to claim 1 wherein the plurality of predetermined time periodscomprise a plurality of time frames on one or more radio frequencies. 3.The communication system according to claim 2 wherein the plurality oftime frames are subdivided into a plurality of phases corresponding to arate of information transmission.
 4. The communication system accordingto claim 1 wherein the monitoring means further comprising:means fordetermining the information transmission time and the idle transmissiontime of the plurality of predetermined time periods; means for summingthe information transmission time and the idle transmission time; andmeans for averaging the information time over the sum of the informationtransmission time and the idle transmission time.
 5. The communicationsystem according to claim 1 wherein the means for reassigning said atleast one of the radio receiver to another of the plurality ofpredetermined time periods includes receiving an over-the-air controlsignal for reprogramming said at least one radio receiver to receiveinformation on another of the plurality of predetermined time perioddesignated by the control signal.
 6. The communication system accordingto claim 5 wherein said at least one radio receiver includes anacknowledge-back transmitting means for transmitting a response to arequest for reassignment, and for responding to a transmitting terminalof the receipt of the control signal for reassigning the radio receiverto another designated predetermined time period.
 7. The communicationsystem according to claim 5 wherein the means for reassigning reassignsthe at least one radio receiver having a traffic level above theestablished threshold value.
 8. The communication system according toclaim 5 wherein the means for reassigning reassigns said at least oneradio receiver having a traffic level below the established thresholdvalue.
 9. The communication system according to claim 1 wherein themeans for reassigning further including:means for selecting a radioreceiver with a traffic level above a threshold value associated withthe radio receiver; means for calculating the traffic level of thepredetermined one of the plurality of time periods assigned to the radioreceiver being selected without including traffic contribution of theradio receiver being selected; means for determining another time periodfor reassigning the radio receiver being selected; and said means forcalculating the traffic level of the determined time period includingthe traffic contribution of the radio receiver being selected whichbalances traffic on the plurality of predetermined time periods.
 10. Ina radio communication system having radio receivers assigned to one of aplurality of predetermined time periods on at least one radio frequency,a method for reassigning the radio receivers, comprising the stepsof:(a) monitoring a level of received information traffic associatedwith each of the plurality of predetermined time periods fortransmitting to at least one of the radio receivers; (b) measuring alevel of traffic associated with one or more radio receivers over one ofthe plurality of predetermined time periods; (c) determining if one ormore of the radio receivers during the one of the plurality ofpredetermined time periods have a traffic level above a threshold value;and (d) reassigning one or more radio receivers to reduce the trafficlevel of the one of the plurality of predetermined time periods when oneor more of the radio receivers have a traffic level above the thresholdvalue.
 11. The method for reassigning radio receivers according to claim10 wherein the step of measuring includes the step of selecting only theradio receivers receiving graphics and alphanumeric type information tobe measured.
 12. The method for reassigning radio receivers according toclaim 10 wherein the step of reassigning radio receivers reassigns theradio receivers having a traffic level below the threshold trafficvalue.
 13. The method for reassigning radio receivers according to claim10 wherein the step of reassigning, comprises:(e) transmitting a servicerequest to selected radio receivers to contact the service provider; (f)waiting a predetermined length of time for a telephone response from auser of the selected radio receiver; (g) transmitting an over-the-aircontrol signal to the radio receivers of the selected radio receiverthat has responded to a reassignment request; and (h) transmitting averification signal during the reassigned predetermined time period forconfirmation of reassignment of the radio receivers.
 14. The method forreassigning radio receivers according to claim 13 wherein step (e)through step (h) communicate with the radio receiver with anacknowledge-back transmitting means for automatically transmitting aresponse to the request for reassignment.
 15. A radio communicationsystem having selective call receivers assigned to a predetermined oneof a plurality of time periods, comprising:a transmitter fortransmitting information during the predetermined one of the pluralityof time periods assigned to at least one selective call receiver; areceiver for receiving information directed to said at least oneselective call receiver, said at least one selective call receiver beingindividually assigned to receive the information during thepredetermined one of the plurality of time periods; a microcomputer formonitoring a level of traffic associated with each of the plurality oftime periods; said microcomputer for measuring a level of trafficassociated with said at least one selective call receiver over thepredetermined one of the plurality of time periods assigned to said atleast one selective call receiver; said microcomputer for identifying ifthe level of traffic associated with said at least one selective callreceiver exceeds a predetermined threshold value during thepredetermined one of the plurality of time periods; said microcomputeralso generating a control signal; said transmitter for transmitting thecontrol signal to said at least one selective call receiver forreassigning said at least one selective call receiver, said at least oneselective call receiver comprising:a receiver for receiving said controlsignal; a decoder, coupled to said receiver, for decoding said controlsignal; and a microcomputer, coupled to said decoder, for reassigningsaid at least one selective call receiver from said predetermined one ofthe plurality of time periods to another of the plurality of timeperiods having a lower level of traffic value associated therewith forreducing the level of traffic in said predetermined one of the pluralityof time periods.